- Medium Speed Data Capture / Control
- General Lab ADC / DAC / Digital IO
- Waveform capture & FFT
- IP Development & prototyping
- Oscilloscope (Option)
- Spectrum analysis (Option)
- 8 x channel 50 kSPS, 16-bit ADC
- 8 x channel 50 kSPS, 16-bit DAC
- 4 x dual port digital IO interfaces (32 GPIO, or 8 SPI, or 8 I2C, or 8 UART or a combination thereof)
- Xilinx Artix XC7A100T – 101,440 logic cells, 4,860 kbit block RAM, 240 DSP48 logic slices, 256MByte external DDR3 SDRAM
- 200MHz 32-bit soft-core Microblaze CPU
- 1GHz Quad core ARM Cortex A-7, 1GByte RAM
- 10/100 Base-T Ethernet socket
- 3 x USB 2.0 Host interfaces
Example External Digital IO Components
- Logic level shifter
- 2 – 12bit ADC
- Audio amplifier
- 4 – 8bit DAC
- IR light detector
- Ultrasonic range finder
- H-Bridge driver
- Stepper Motor Driver
- Impedance analyzer
- 4 – 12 bit ADC
- Capacitive input buttons
- 3 axis gyroscope
- IO expansion module
- 3 axis digital compass
- Thermostat control board
- Real time clock / calendar
- Bluetooth interface
- LCD serial interface
- Ultrasonic range finder
- RS232 with D-type connector
- High speed isolated communications
- USB interface
- OLED display 96×64 RGB
- 3 Axis accelerometer
- 3 axis MEMS accelerometer
- 4 – 4.8kHz – 24 bit ADC
- 8 – 12bit DAC
- 2 axis joystick
- Network Interface Controller (Ethernet)
- ZigBee / MiWi
- SD Card interface
- WiFi Interface
- Microphone with adjustable gain
- Thermocouple with wire
OpenIO Labs Medium Speed Multi-Channel Data Acquisition and Control System integrates 8 channel, 16-bit, 50kSPS ADC, 8 channel, 16-bit 50kSPS DAC with a Xilinx Artix XC7A100T FPGA and a 1GHz Quad core ARM Cortex A-7 Processor. The combined system can process in real-time analogue input and output signals that are in excess of 25kHz.
The ADC is designed to sample medium bandwidth analogue signals. It is optimised for wide input bandwidth, high sampling rate, excellent linearity and low power. The ADC core includes multiple successive approximation architecture. Each ADC has buffered inputs and user-selectable input ranges. The ADC uses an SPI serial interface to the Xilinx Artix FPGA, which is also used for configuration and control of the dual ADC.
The DAC is nominally configured with a 50kSPS sampling rate. The analogue output bandwidth is in excess of 25kHz. Configuring and controlling of the DACs is achieved through the use of a SPI serial communication protocol from the FPGA to the DACs.
The FPGA is a 101,440 logic cell Xilinx Artix FPGA that includes 240 DSP48 logic slices to implement high speed DSP functions. The FPGA has internal RAM in excess of 4.7Mb and a multi-port external DDR3 SDRAM with 256MBytes storage.
Pre-defined hardware accelerators included in the FPGA include FFT, FIR filters, IIR filters and a range of statistical processing and analysis functions. Each of the hardware accelerators can be accessed simply via the ScriptML™ interface to the FPGA and the IOI-MS-DAS-8 unit. In addition, user defined DSP functions are implemented in VHDL or Verilog and loaded into the FPGA via the CPU and the OpenIO Labs server. User defined DSP elements are created using the Xilinx Vivado FPGA development suite.
The FPGA implements four dual-port digital IO interfaces with each of the dual-ports software configurable to support any of I2C, SPI, UART or GPIO using a switching matrix within the FPGA and controlled via the ScriptML™ application control protocol.
An external 256MByte DDR3 SDRAM memory is attached to the FPGA and can be used in a multi-port configuration to allow the memory to be used by multiple simultaneous applications.
The embedded processor is attached to the FPGA via a USB 2.0 high-speed interface, allowing data transfer up to 480 Mbps. The embedded processor includes a 4-core ARM CPU, a USB-2.0 interface available for user extension peripherals and a 10/100 Base-T Ethernet interface.
A FLASH memory and a PROM memory are used for FPGA image storage for booting and for the storing of device data such as the ADC / DAC calibration data. The device calibration data is loaded via a factory calibration and configuration procedure.
The main software interface to the IOI-MS-DAS-8 is via the OpenIO Labs ScriptML™ interface. ScriptML™ allows full user control of the IOI-MS-DAS-8 using simple scripting commands written in the language of preference (examples of supported languages are C, Python and Java). The user-defined scripts allow full access to the control and operation of the IOI-MS-DAS-8 using either native language commands or using the hardware accelerators (pre-defined or user defined). Using ScriptML™, the user is able to simply and efficiently create advanced applications with the minimal time to setup and configure the system and without the need to load complex drivers into the target host system.
The IOI-MS-DAS-8 has an external trigger signal that can be either a source or a sink. Using the external trigger multiple IOI-MS-DAS-8 units can be chained together to provide a set of synchronised signals.
The IOI-MS-DAS-8 has an internal Xilinx MicroBlaze soft-core 32-bit CPU. The CPU connects to all of the internal processing fabric using the AXI interface bus. The CPU allows additional user control of the internal processing functions of the IOI-MS-DAS-8 and interfaces to the end user via the ScriptML™ protocol.